TRELU

Tile Operation Diagram

TRELU tile operation

Introduction

Elementwise ReLU of a tile.

Math Interpretation

For each element (i, j) in the valid region:

\[ \mathrm{dst}_{i,j} = \max(\mathrm{src}_{i,j}, 0) \]

Assembly Syntax

PTO-AS form: see PTO-AS Specification.

Synchronous form:

%dst = trelu %src : !pto.tile<...>

IR Level 1 (SSA)

%dst = pto.trelu %src : !pto.tile<...> -> !pto.tile<...>

IR Level 2 (DPS)

pto.trelu ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>)

C++ Intrinsic

Declared in include/pto/common/pto_instr.hpp:

template <typename TileData, typename... WaitEvents>
PTO_INST RecordEvent TRELU(TileData& dst, TileData& src, WaitEvents&... events);

Constraints

  • Implementation checks (A2A3):
  • TileData::DType must be one of: half, float, int32_t.
  • Tile layout must be row-major (TileData::isRowMajor).
  • Tile location must be vector (TileData::Loc == TileType::Vec).
  • Static valid bounds: TileData::ValidRow <= TileData::Rows and TileData::ValidCol <= TileData::Cols.
  • Runtime: src and dst tiles should have the same validRow/validCol.
  • Implementation checks (A5):
  • TileData::DType must be one of: half, float, int32_t.
  • Tile layout must be row-major (TileData::isRowMajor).
  • Tile location must be vector (TileData::Loc == TileType::Vec).
  • Static valid bounds: TileData::ValidRow <= TileData::Rows and TileData::ValidCol <= TileData::Cols.
  • Runtime: src and dst tiles should have the same validRow/validCol.
  • Valid region:
  • The op uses dst.GetValidRow() / dst.GetValidCol() as the iteration domain; src/dst are assumed to be compatible (not validated by explicit runtime checks in this op).

Examples

#include <pto/pto-inst.hpp>

using namespace pto;

void example() {
  using TileT = Tile<TileType::Vec, float, 16, 16>;
  TileT x, out;
  TRELU(out, x);
}

ASM Form Examples

Auto Mode

# Auto mode: compiler/runtime-managed placement and scheduling.
%dst = pto.trelu %src : !pto.tile<...> -> !pto.tile<...>

Manual Mode

# Manual mode: bind resources explicitly before issuing the instruction.
# Optional for tile operands:
# pto.tassign %arg0, @tile(0x1000)
# pto.tassign %arg1, @tile(0x2000)
%dst = pto.trelu %src : !pto.tile<...> -> !pto.tile<...>

PTO Assembly Form

%dst = trelu %src : !pto.tile<...>
# IR Level 2 (DPS)
pto.trelu ins(%src : !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>)